Digital VLSI Design and Simulation with Verilog
Digital VLSI Design and Simulation with Verilog
Sanjeet K. Sinha, Govind S. Patel, Suman Lata Tripathi, Sobhit Saxena
Details
- OL Work ID
- OL26813731W
Subjects
Electronic circuitsIntegrated circuits
Sanjeet K. Sinha, Govind S. Patel, Suman Lata Tripathi, Sobhit Saxena