Parasitic Substrate Coupling in High Voltage Integrated Circuits

Parasitic Substrate Coupling in High Voltage Integrated Circuits
Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese
Details
- OL Work ID
- OL20903274W

Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese